arch-hdl-lang

arch-hdl-lang / arch-com

Public

ARCH hardware description language and compiler

18
2
100% credibility
Found Apr 17, 2026 at 18 stars -- GitGems finds repos before they trend. Get early access to the next one.
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AI Analysis
SystemVerilog
AI Summary

A compiler for the ARCH hardware description language that generates readable SystemVerilog from simple, AI-friendly descriptions with built-in safety checks and simulation support.

How It Works

1
🔍 Discover ARCH

You hear about ARCH, a simple way to describe electronic circuits that catches mistakes early and works great with AI helpers.

2
📝 Describe Your Circuit

You write a plain text file outlining your hardware idea, like a traffic light or counter, using clear keywords for states and connections.

3
✅ Check for Errors

You verify your design instantly, spotting width mismatches or unsafe clock crossings before they become problems.

4
🔧 Build to Standard Format

You transform your description into clean, professional code that any chip tool can use right away.

5
Test It Out
⚡
Fast Simulation

Run a built-in test to see your circuit behave exactly as expected.

🔗
Real Tools

Plug into existing simulators for deeper checks.

🎉 Circuit Ready!

Your safe, verified hardware design is complete and ready to build into a real chip.

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Star Growth

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AI-Generated Review

What is arch-com?

arch-com compiles ARCH, a SystemVerilog front-end that eliminates HDL pitfalls like implicit width casts and clock domain errors. Write concise designs with explicit `.trunc()` ops, typed `Clock` safety, and keywords like `fsm` or `fifo` that auto-generate assertions and SVAs—no more unbalanced blocks or missing sensitivity lists. CLI commands like `arch build design.arch` spit out readable RTL for Verilator, Vivado, or Yosys, with sim support for C++ or cocotb testbenches.

Why is it gaining traction?

It makes AI-generated RTL reliable: LLMs can't produce invalid structs thanks to named endings and single-driver rules, plus `todo!` skeletons for unsure parts. Built-in CDC gray-coding and exhaustive FSM coverage beat manual SV boilerplate, while keeping full EDA compatibility. Arch hardware acceleration fans appreciate seamless integration with existing flows, sans the usual debug grind.

Who should use this?

RTL engineers building FIFOs, FSMs, or RISC-V peripherals who hate SV width bugs or CDC mishaps. AI-assisted hardware teams generating AXI buses or regfiles via arch github copilot cli. Arch community repo users verifying with Verilator before synthesis.

Verdict

Early alpha (18 stars, 1.0% credibility) with strong docs, E203 benchmarks, and 64 tests—prototype your next design here, but pair with mature tools for prod until adoption grows.

(187 words)

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