Yii2004

Yii2004 / TinyCoDesign

Public

Minimal FPGA hardware/software co-design demo with UART protocol, scratchpad memory, and an int8 dot-product accelerator, plus Python/C++ runtimes.

accelerator cpp fpga hardware-software-codesign python
11
0
100% credibility
Found May 13, 2026 at 11 stars -- GitGems finds repos before they trend. Get early access to the next one.
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AI Analysis
Verilog
AI Summary

TinyCoDesign is an open-source demonstration of software controlling a simple math accelerator on a specific FPGA board via serial connection, with simulators and examples in Python and C++ for testing.

How It Works

1
🔍 Discover TinyCoDesign

You stumble upon this fun project online that lets you control a tiny hardware math helper.

2
💻 Try it on your computer

Download the files and run pretend tests right on your regular computer to see how it works.

3
✨ See the magic happen

Watch it print messages or crunch simple numbers super fast, just like a preview of real power.

4
Pick your adventure
🖥️
Stay simulated

Keep experimenting safely on your computer with no extra gear.

🔌
Connect real board

Get a small circuit board and plug it into your computer with a USB cable.

5
🚀 Send your first job

Type a simple message or numbers, and send them to your hardware helper.

6
💡 Watch it light up

See tiny lights blink as it works, showing it's busy then done.

✅ Get your speedy results

Receive the calculated answers back quickly, feeling the thrill of custom hardware speed.

Sign up to see the full architecture

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Star Growth

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AI-Generated Review

What is TinyCoDesign?

TinyCoDesign delivers a minimal FPGA hardware/software co-design demo on the DaVinci Pro 100T minimal FPGA board, using Verilog for a UART protocol, scratchpad memory with two 1024-byte int8 banks, and a tiny dot-product accelerator. It lets you send commands from host Python or C++ runtimes over UART, schedule jobs on the accelerator, and get results back through the same channel—simplifying the full control-data loop without DDR or complex NPUs. Users get simulator-backed testing plus real-board demos for print, dot-product, and tiled matmul.

Why is it gaining traction?

This stands out for its bare-bones scope: no generated Vivado projects or build cruft, just source RTL, constraints, and editable Python/C++ packages you compile yourself. The built-in simulator runs CLI commands like "dot 1,2,-3 5,-2,7,1" or Python matmul without hardware, hooking developers who want quick co-design experiments over heavyweight frameworks. Cross-platform serial support and self-checking testbenches make iteration fast.

Who should use this?

FPGA tinkerers prototyping int8 accelerators on Artix-7 boards, embedded students learning UART protocols and scratchpad flows, or hardware/software co-design researchers testing tiled dot-product kernels before scaling up. Ideal for those with a minimal FPGA board who skip bloated toolchains.

Verdict

Grab it as a solid starter demo for minimal co-design—11 stars and 1.0% credibility score reflect its niche early stage, but strong docs, tests, and simulator make it reliable for learning. Skip if you need production-scale or non-Artix targets.

(198 words)

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