TONGJI-EDA-LAB

TONGJI-EDA-LAB / RTL-CLAW

Public

This project is primarily aimed at showcasing an EDA toolchain based on the OpenClaw framework, in which our own research work is also demonstrated. The project will be continuously updated to support the integration of more of our research outcomes, open-source tools, and commercial tools into the toolchain in the form of additional plugins.

25
2
100% credibility
Found Mar 31, 2026 at 25 stars -- GitGems finds repos before they trend. Get early access to the next one.
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AI Analysis
Verilog
AI Summary

RTL-CLAW is a research framework that employs AI agents to automate front-end integrated circuit design processes including RTL analysis, partitioning, optimization, verification, and synthesis.

How It Works

1
🔍 Discover RTL-CLAW

You hear about this university research tool that uses smart AI helpers to automate tricky chip design tasks like splitting and improving code.

2
📥 Get the project

You download the simple package from the researchers' page and prepare a spot on your computer for your designs.

3
🚀 Launch the helper

You run a quick setup to start the AI service and create folders for your work, making everything ready in moments.

4
🌐 Open the chat room

You go to a webpage on your computer and use a private code to step inside the secure conversation space.

5
📁 Add your files

You drop your chip design files into the work area, ready for the AI to handle.

6
💬 Give instructions

You simply tell the AI what to do, like 'split this design file' or 'make it better', and watch it work its magic.

✅ Get perfect results

Your designs come back improved, split neatly, or verified, saving you hours and speeding up your chip project.

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Star Growth

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AI-Generated Review

What is RTL-CLAW?

RTL-CLAW is a Docker-based EDA toolchain that automates front-end IC design flows using AI agents built on the OpenClaw framework. It handles Verilog RTL analysis, partitioning, optimization via partition-opt-merge, verification, testbench generation, and logic synthesis targeting ASAP7nm tech library. Developers get a chat interface at localhost:18789 to command agents for tasks like splitting traffic light controller Verilog files, with outputs in a workspace directory.

Why is it gaining traction?

It stands out by wrapping AI agents around open-source EDA tools for natural language-driven automation, skipping manual scripting for RTL tweaks. Extensible plugins let you add research outcomes or commercial tools, and the quick Docker Compose setup with CLI onboarding makes prototyping fast. Low barrier for project github example flows appeals to those eyeing AI in chip design.

Who should use this?

EDA researchers or IC design students prototyping AI-automated RTL workflows, especially for partition-opt-merge on small Verilog modules. Suits academics from Tongji or CUHK affiliates integrating additional open-source synthesis like Yosys, but skip if you need production-scale back-end flows.

Verdict

At 25 stars and 1.0% credibility score, it's an early research demo with solid README and technical report, but lacks full license, tests, and published modules—build locally first. Worth forking for project evaluation if you're into AI-agent EDA experiments; otherwise, monitor the roadmap for OpenROAD integration.

(198 words)

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