Haouo

Haouo / DAE-Pipeline-CPU

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An small in-order, decoupled frontend-backend, pipeline CPU which implements RV32I_Zicsr and boots FreeRTOS.

19
1
89% credibility
Found May 28, 2026 at 19 stars -- GitGems finds repos before they trend. Get early access to the next one.
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AI Analysis
C
AI Summary

DAE Pipeline CPU is an educational project that teaches how computer processors are designed. It presents a readable RISC-V processor that starts from simple textbook concepts and evolves into a more robust design, demonstrating real-world challenges like handling memory delays, branch predictions, and interrupt handling. The project includes a complete mini-computer system with memory and peripherals, along with test suites and a FreeRTOS demo that lets learners watch a CPU execute instructions and manage multiple tasks.

How It Works

1
📚 You discover a learnable CPU design

You find a project that explains how computer processors work, starting from simple textbook ideas and building up to real-world complexity.

2
🔍 You explore the architecture

The project shows you how a CPU processes instructions in stages, like an assembly line, with special handling for tricky situations like branches and memory delays.

3
🧩 You see how everything connects

The project includes a complete mini-computer system with memory, timers, and communication ports that all work together with the CPU.

4
You choose your learning path
✅
Run standard tests

Execute the built-in test suite and watch hundreds of CPU instructions execute correctly, proving everything works.

🚀
Try the FreeRTOS demo

Load a tiny operating system that runs multiple tasks at once, showing how the CPU handles competing priorities.

5
👀 You watch the simulation run

The CPU comes alive in your terminal as instructions flow through each stage, with output appearing just like a real computer would produce.

🎓 You understand how CPUs really work

You've seen firsthand how the gap between textbook simplicity and real processor complexity is bridged through careful design and clever techniques.

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Star Growth

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AI-Generated Review

What is DAE-Pipeline-CPU?

A complete RISC-V system that combines a readable CPU pipeline with a full software stack. The project implements a decoupled frontend/backend architecture—an in-order pipeline where the fetch/decode front end feeds into a queue that the execute/memory/writeback back end pulls from. It supports the RV32I base instruction set plus the Zicsr extension for control registers, and boots FreeRTOS as a real demonstration.

The C code handles the software side: a minimal SoC with UART, a timer, interrupt controller, and DRAM. A Verilator testbench simulates the RTL pipeline while the C code runs as a DPI bridge. You get boot ROM, interrupt handling, ELF loading, and a working FreeRTOS demo with multiple tasks communicating via semaphores.

Why is it gaining traction?

The hook is readability over performance. Most RISC-V implementations are either production-grade (complex) or toy examples (too simple). This project sits in between—it shows how a textbook five-stage pipeline evolves when you add cache stalls, traps, and interrupts without jumping to out-of-order complexity.

The decoupled design with a scoreboard for hazard detection and epoch-tagged tokens for recovery gives you production ideas in an accessible form. Running FreeRTOS on top proves the ISA compliance is solid, and the riscv-tests suite validates it nightly.

Who should use this?

Computer architecture students who want to see textbook concepts implemented end-to-end. The documentation explicitly maps design decisions to the textbook five-stage pipeline.

Embedded systems developers exploring RV32I for custom controllers will find the peripheral code and FreeRTOS port useful as reference material.

RISC-V implementers evaluating decoupled pipeline patterns will appreciate the explicit scoreboard and IR queue design.

Verdict

A solid educational RISC-V system with real software running on it. The credibility score of 0.9% reflects its niche audience and small star count, not quality—the code is well-structured with clear docs and a working test suite. It is not production-ready but excels as a teaching tool. If you want to understand how pipelines handle hazards and traps, this is worth studying.

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