AliSahafi

AliSahafi / Analog_OpenSource_ihp

Public

This is a complementary extension to the https://hub.docker.com/r/hpretl/iic-osic-tools Docker image, adding support for RF simulations and a digital Verilog-to-GDS flow.

12
3
100% credibility
Found Mar 02, 2026 at 12 stars -- GitGems finds repos before they trend. Get early access to the next one.
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AI Analysis
Python
AI Summary

This project offers a browser-accessible virtual workspace for open-source design and simulation of analog, RF, and digital integrated circuits using a specific manufacturing kit.

How It Works

1
🔍 Discover the Chip Workshop

You find this free toolkit that lets hobbyists and learners design and test tiny electronic chips for radios and digital gadgets.

2
📦 Get It Ready

Download the package and start your personal virtual workshop on your computer with simple preparation steps.

3
🚀 Launch the Studio

Your chip design environment springs to life, accessible right in your web browser like a remote desktop.

4
🔑 Step Inside

Log in with the easy default password to explore the full set of drawing and simulation tools.

5
Choose Your Path
📡
RF Simulations

Set up and run tests for inductors and other radio components to see how they perform.

🔌
Digital Designs

Describe your logic circuit and automatically generate a blueprint ready for making.

6
⚙️ Create and Test

Use the handy programs to draw shapes, run simulations, or convert descriptions into layouts.

7
📊 See Amazing Results

Watch as colorful graphs of performance pop up, or admire your polished chip blueprint.

🎉 Design Complete!

You now have professional-looking chip designs and simulation data to share or build upon.

Sign up to see the full architecture

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Star Growth

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AI-Generated Review

What is Analog_OpenSource_ihp?

This Docker-based complementary extension builds on the hpretl/iic-osic-tools image, adding analog, RF simulation support and a fixed digital Verilog-to-GDS flow for the IHP SG13G2 open-source PDK. Developers get a ready-to-run container with browser-accessible GUI for tools like setupEM, EMStudio, and Palace 3D EM sims, plus one-command scripts like verilog2gds for RTL-to-layout and Python-based S-parameter plotting for inductors. It solves PDK incompatibilities that break LibreLane flows and missing RF meshing in the base image.

Why is it gaining traction?

As a complementary product extension example, it patches real-world gaps—like IHP PDK corner mismatches and absent tapcells—for seamless RFIC workflows and digital signoff, without manual compiles. The hook is instant browser VNC access to KLayout, Verilator linting, and full-timing analysis via simple CLI flags like --utilization 40 or --full-timing. No more fighting Docker layers or sourcing gmsh; just build once and simulate.

Who should use this?

RFIC designers targeting IHP SG13G2 for inductor meshing and Palace sims, or digital teams needing Verilog/VHDL-to-GDS on open PDKs without endcap hacks. Ideal for mixed-signal devs prototyping SPI masters or sparse layouts at low utilization, especially those extending hpretl/iic-osic-tools flows.

Verdict

Grab it if you're on IHP—docs are solid with examples, and the complementary digital flow works out-of-box despite 10 stars and 1.0% credibility score. Still early; test on non-trivial designs before production, as VHDL support is educational-only.

(198 words)

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